Level shifters are circuits for converting an input signal having a first voltage amplitude into an output signal having a second voltage amplitude different from the first voltage amplitude. Typically, the amplitude is converted by fixing the lower potential side and converting the potential at the higher potential side. Level shifters are widely used in integrated circuits where more than one type of circuits, each having an operation voltage different from that of others, are integrated together.
A common application for level shifters is shifting the voltage of a signal transferred between an IO circuit and a core circuit in an integrated circuit device. Traditionally, the IO operation voltage was compatible with the core operation voltage. However, with the shrinking of VLSI circuits, the operation voltages of core circuits have steadily been lowered, while the IO operation voltages have stayed relatively steady, so that currently, core operation voltages are typically much lower than the IO operation voltages. For example, in deep micron technology, the core operation voltages have dropped to about 0.9V to about 1V, while the IO operation voltages are still about 1.5V to about 3.0V. Therefore, a signal needs to be level-shifted up before it is transmitted from a core circuit to an IO circuit, or level-shifted down before it is transmitted from an IO circuit to a core circuit.
FIG. 1 illustrates a conventional cross-latch level shifter circuit that converts an input signal with an amplitude of VDD, which is, e.g., a core operation voltage, to a signal with an amplitude of VDDIO, which is, e.g., an IO operation voltage that is higher than VDD. Node 102 is a power supply node at power supply voltage VDDIO. Node 104 is at VSS, typically a ground potential or at 0V. Node 106 is a signal input node and node 108 is a signal output node. The input signal voltage at node 106 switches between 0V and VDD. If the input signal voltage at node 106 is 0V, NMOS transistor 114 is turned off, so that its drain voltage at node 124 is high. Inverter 118, whose input at node 106 is low (0V), outputs a high voltage (VDD) at its output, which is connected to node 122. Because the voltage at node 122 is high, NMOS transistor 116 is turned on, thus pulling down the output voltage at node 108. Conversely, if the input signal at node 106 is VDD, NMOS transistor 114 is turned on so that its drain voltage 124 is at a low voltage. The voltage at node 122 is converted to low by inverter 118 so that NMOS transistor 116 is turned off, and the output voltage at node 108 is pulled up by PMOS transistor 112 (which forms a complementary pair with PMOS transistor 110) to VDDIO. Therefore, the input signal with the amplitude of VDD is shifted to VDDIO.
There are also other types of level shifters such as charge-pumped level shifters. However, all these conventional level shifters suffer from a common problem. Their operation speeds are typically low, and are often less than about 1 GHz, for example, conventional level shifters can only operate between 200 MHz and 800 MHz. They are thus not suitable for high-frequency operations. In addition, the conventional level shifters cannot be ported between different specifications, which means that the level shifters need to be modified for different IO operation VDDIOs such as 1.2V, 1.5V, 1.8V, 2.5V, and the like. A further problem is that the switching noise current flowing to VSS (node 104) is high. What is needed, therefore, is a novel level shifter for overcoming the above-described shortcomings in the prior art.